1. Field of the Invention
The present invention relates to techniques of data reading in a semiconductor memory device.
2. Description of Related Art
Semiconductor memory devices such as a DRAM (Dynamic Random Access Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory and the like are known. In general, at the time of data reading in such a semiconductor memory device, a read-out level read out from a memory cell is compared with a predetermined reference level and thereby a data stored in the memory cell is judged (determined).
Japanese Laid-Open Patent Application JP-P2005-209304A describes a technique in which data is judged by using a first reference potential and a second reference potential. According to the technique, the settings of the first reference potential and the second reference potential are designed to improve data-judgment precision in a sense amplifier circuit. The sense amplifier circuit includes: a first sense amplifier that performs the sense operation by comparing a data potential read out from a memory cell with the first reference potential; and a second sense amplifier that performs the sense operation by comparing the data potential with the second reference potential. The data judgment (“0” or “1”) is achieved by the collaboration of the first sense amplifier and the second sense amplifier. Then, one kind of read data corresponding to a result of the data judgment is output from the sense amplifier circuit.
The inventor of the present application has recognized the following points with regard to the semiconductor memory device.
After a data is programmed to a memory cell, there is a possibility that the data stored in the memory cell varies in time. In a case of an EEPROM, for example, a threshold voltage of a memory cell transistor can vary due to electrons coming into and leaking from a floating gate. This leads to variation in the stored data (so-called “data dissipation” or “data corruption”). The variation in the stored data causes malfunction of a microcomputer provided with the semiconductor memory device.
As a countermeasure against the data dissipation, an ECC (Error Correction Code) circuit may be employed. The ECC circuit is capable of detecting a certain number of error bits in a data read out from memory cells and correcting some of the error bits. However, if there exist error bits more than the correctable number of bits in the read-out data, even the ECC circuit cannot correct the read-out data. In this case, the malfunction of the microcomputer still occurs and thus the microcomputer fails. Even when the ECC circuit is applied to the semiconductor memory device described in the above-mentioned patent document, the result is the same. If there exist error bits more than the correctable number of bits in the one kind of read data output from the sense amplifier circuit, the correction of the read data is no longer possible.
A technique that can reduce the malfunction of microcomputer caused by the data dissipation is desired.